1. Field of the Invention
The present invention generally relates to integrated circuits (ICs), and more particularly to interconnect structures, including multilevel interconnect structures, in which an advanced plasma process is utilized to enable a reduction of critical dimension non-uniformity post lithographic processing; thus improving liner and Cu seed conformality for desired device/interconnect performance, reliability, and functionality.
2. Description of the Prior Art
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit including chips (e.g., chip back end of line, or “BEOL”), thin film packages and printed circuit boards. Integrated circuits can be useful for computers and electronic equipment and can contain millions of transistors and other circuit elements that are fabricated on a single silicon crystal substrate. For the device to be functional, a complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the device. Efficient routing of these signals across the device can become more difficult as the complexity and number of integrated circuits are increased. Thus, the formation of multi-level or multi-layered interconnection schemes such as, for example, dual damascene wiring structures, have become more desirable due to their efficacy in providing high speed signal routing patterns between large numbers of transistors on a complex semiconductor chip. Within the interconnection structure, metal vias run perpendicular to the silicon substrate and metal lines run parallel to the silicon substrate.
Presently, interconnect structures formed on an integrated circuit chip consists of at least about 2 to 8 wiring levels fabricated at a minimum lithographic feature size designated about 1× (referred to as “thinwires”) and above these levels are about 2 to 4 wiring levels fabricated at a width equal to about 2× and/or about 4× the minimum width of the thinwires (referred to as “fatwires”). In one class of structures, the thinwires are formed in a low dielectric constant (κ) organosilicate (SiCOH) or polymeric dielectric inter-level dielectric (ILD) layer, and the fatwires are made in a silicon dioxide ILD having a dielectric constant of about 4.0. FIG. 1 depicts a cross-sectional view of a conventional 5-level metal BEOL interconnect structure showing two thinwire and three fatwire levels.
One of the many challenges associated with the fabrication of the thinwires for 90 nm and beyond CMOS BEOL technologies is the reliable printing of ground rule features (≦140 nm) using 193 nm lithography. To enable lithographic processing in this regime Si-containing resist materials have been and are being considered. These materials, however, while capable of achieving target feature sizes for the 90 nm and beyond (e.g., 45 nm line thicknesses) BEOL technology nodes, have severe issues with post lithographic CD non-uniformity or so-called “line edge roughness” (LER). FIG. 2 is a CD SEM image of an example 200 mm 65 nm node M1 comb serpentine structure (post lithography) utilizing a Si-containing resist material and depicts a severe CS non-uniformity (LER). Such post lithographic image roughness or LER is readily transferred during via or trench creation (plasma etch processing); rendering liner and seed conformality difficult. From a lithography perspective, there are a few options available to address such LER for a specific resist material. These might entail changing the resist material formulation to increase photoacid diffusion or adjusting the molecular weight of the polymer. However, since these changes also affect the lithographic capability of the resist, the most common attempts to reduce LER involve post lithography processes such as a post-development bake to flow the resist and smooth the edges, using a resist overcoat, or more complex processes where very thin films of polymers are chemically bound to the resist surface in an attempt to smooth the roughness.
Typically, however, if there is severe LER post lithography for a given resist material, the aforementioned techniques only manage to achieve minimal improvement in CD uniformity.
It would be highly desirable to provide a BEOL interconnect structure of, e.g., the dual damascene type, in which an advanced plasma process is utilized to reduce post lithographic CD non-uniformity (“line edge roughness”) in both via and trench structures for potentially multiple OSG or polymeric-based ILD materials.
It would further be highly desirable to provide a BEOL interconnect structure in which there is improved liner and seed conformality on ILD sidewalls.
It would further be highly desirable to provide a BEOL interconnect structure of improved device and BEOL interconnect functionality, reliability, and performance.